Overview of Conventional Electronic High-Speed Analog-to-Digital Conversion
Overviews of conventional electronic ADC techniques and their state-of-the-art are available in [4-9]. Two main Analog to Digital Converter (ADC) characteristics are the sampling rate (or signal bandwidth), and the quantization resolution, expressed in bits. To extract the full information available in an analog signal, one has to sample it at least as fast as the “Nyquist Rate”, a rate equal to twice its maximum frequency. It follows that a high sample rate is required in order to reproduce large bandwidth signals. High quantization resolution permits to lower the quantization noise. Practical implementations of ADCs add extra noise and distortion to the signal, further limiting the actual quantization resolution. In the presence of noise, the relevant quantity that captures the actual resolution is called Effective Number Of Bits (ENOB), namely the number of bits (resolution) that an ideal ADC would have to have, such that its quantization noise would be equal to the total noise generated by the actual ADC (including both the quantization noise and the other sources of noise and distortion). Notice that fractional ENOBs are also allowed. Electronic (ADC) technology cost-effectively provides the bulk of ADC conversion required for mass applications, based on switched-capacitor CMOS mixed-signal circuitry. As technology improves, successively more powerful ADCs have been introduced; however, achieving a large ENOB for signals of multi-GigaHz wideband signals is an outstanding challenge.
While progress in ADC electronic technology has been steady, the limitations of electronic technology are most evident for high-end ADC systems, exceeding sampling rates of a few Giga samples per second (GS/s). In this regime as few as 3 bits of effective resolution are achievable only at high complexity and effort, as evident in the high cost and large size of 10-40 GS/s sampling oscilloscopes (which actually digitize repetitive waveforms rather than real-time arbitrary waveforms, hence their performance is better than a hypothetical ADC at the same sampling rate). Similarly, the ADC systems used for capturing RF waveforms in Electronic Warfare (EW) systems are bulky, occupying whole racks.
There are multiple classes of ADCs, the main ones being                (i) Flash ADCs        (ii) Successive Approximations Register (SAR) ADCs        (iii) Pipelined ADCs        (iv) Oversampling ADCs, such as Σ-Δ ADCs.        
The most dominant limitation of high-speed A/D conversion is the jitter and phase-skew of the sampling clock, degrading the sampling performance of the Track & Hold (T&H) ADC front-ends. Other limitations of the T&H circuitry pertain to the transients of the electronic circuitry, parasitics (e.g. stray capacitances), offsets and gain variations, component mismatches, nonlinearities, couplings between sampling and sampled signals, the detrimental effect of all of which compounds as ADC speed is increased.
For high-speed applications, which are our interest here, flash ADCs are typically used, often in conjunction with time-interleaving, as described below.
In flash ADC systems the T&H front-end is followed by a quantizer, realized as a parallel bank of comparators, in effect comparing the input signal against a sequence of equally-spaced threshold comparators representing the ADC levels. Each comparator acts like a 1-bit ADC, in effect digitally generating the sign of the difference between its two inputs signal (the RF signal under test and the voltage threshold). The technology of these comparators, considered individually, is relatively well-developed (one of the comparator impairments is the so-called metastability of the latch circuitry). It turns out that comparator speeds are currently not the bottleneck of flash ADC systems, however significant additional degradation arises upon “gluing together” multiple comparators to form a complete flash-quantizer: The generation and stability of the set of threshold voltages and the undistorted distribution of replicas of the signal under test to the comparator manifest as an additional performance-limiting factors for high-speed ADCs.
Finally, given ADCs of a certain speed, a faster ADC system may be generated by time interleaving the slower modules, in effect dividing the train of samples under test into m interleaved sub-trains and using a bank of slower ADCs (each operating at a m-times slower sampling rate) in order digitize each of the sampling sub-trains (notice however that the front-end T&H of each such ADC should be able to capture the full signal bandwidth). The issues limiting the performance of such Time-Interleaved ADC (TI-ADC) are the control and matching of the timing phases, gains and offsets of the individual ADCs.
We end up this review section by introducing conceptual signal-theoretic block diagrams for the main types of ADCs which our invention will disclose photonic realizations thereof. We start with a key building block, the comparator (CMP), which is a system with two analog scalar S, R and a Boolean output bε(0,1) such that b=1 if S>R, b=0 otherwise. In this disclosure we also consider a comparator with a single input S, implying that the second input is “grounded” R=0, i.e. b=1 if S>0, b=0 if S≦0. Hence, such single-input comparator is a sign-detector, alternatively referred to in this disclosure as slicer, or 1-bit ADC. The three named terms are then synonymous. We also use comparators with bipolar Boolean b=±1 outputs. A single input comparator with bipolar output is then described as b=sign{S}. A two-input comparator with bipolar output may be described in terms of a single input comparator as b=sign {S−R}.
Actually an ADC which is not a compound structure, typically a flash ADC, is the cascade of a Track & Hold module otherwise known as Sample & Hold (S&H), wherein sampling is performed, followed by a Quantizer, followed by an Encoder producing the final bit-string.
Generally, the logical block diagram of a Photonic ADC (PADC) follows a logical block diagram of an Electronic ADC as known in the art. Thus, this overview is relevant to both ACD and PADC.
The current invention details ways of implementing the PADC using optical and electro-optical components instead of at least some of the electronic components used in ADCs.
We next survey four types of ADCs and PADC, focusing on their quantizers, i.e. assuming the sample is held to a fixed value, essentially treating it as a scalar input:
FIG. 1 schematically depicts a block diagram of a generic flash ADC as known in the art.
A flash ADC is described in FIG. 1. The signal under test Φ (which could conventionally be a voltage—an electrical potential (in the PADC according to the invention, Φ is represented by an optical phase, as would be discussed below) is split N=2b ways, with b the number of bits and N the number of levels, and compared in parallel to a sequence of levels (thresholds) {θ(1), θ(2), . . . , θ(N)}={g1θ, g2θ, . . . , gNθ} where θ is a reference signal and {gn}n=1N are scaling factors. Typically, {θ(1), θ(2), . . . , θ(N)} form an arithmetic sequence, i.e. they are equally spaced.
In a conventional electronic implementation of the flash converter 100, the levels θ(n)=gnθ are generated by means of a voltage divider ladder, with θ the reference voltage feeding the ladder and g, the n-th voltage division factor. In our PADC realization the thresholds {θ(1), θ(2), . . . , θ(N)} are in the angular domain—optically generated reference phases. The quantizer section then generates, in parallel (hence the name “flash”) N decisions described by the vector of bipolar bits B={b1, b2, . . . , bN}={sign{Φ−θ(n)}}n=1N. In the absence of errors, B is of the form B={+1, +1, . . . , +1, +1, −1, −1, . . . , −1}, i.e. it comprises contiguous+1-s followed by contiguous −1s, assuming that the scaling factors {gn}n=1N are ascending. Typically, for a mid-rise quantizer (which has a transition right at zero) θn=(n−N/2)Δ, n=1, 2, . . . N−1 and for a mid-tread quantizer θn=[n−(N+1)/2]Δ, n=1, 2, . . . N−1, Δ=FS/N=FS/2b the step-size or LSB. The encoder section consists of the so-called “thermometer code” generating an indication of the element position whereat the sign is flipped, which is expressed in binary (as generated by the encoding section hardware, from the B vector input {b1, . . . bN}), yielding the ADC decision for the given signal under test Φ. This element position is the index of the decision region within which the signal under test Φ falls.
FIGS. 2a and 2b schematically depicts a Successive Approximations Register (SAR) ADC as known in the art.
A block diagram of a SAR ADC 120 is described in FIG. 2a(i).
The output of a Digital to Analog Converter (DAC) is subtracted 121 off the signal under test 122, and then the difference 123 is quantized to b bits by a b-bits ADC 124. The ADC decision is presented to the SAR logic 125 which generates a control word 126 driving the B-bits DAC 127, closing the loop.
The output 128 has B bits wherein B>b, or B=b+d, with d>0.
In electronics invariably we have b=1, i.e. the ADC 124 is actually a highly accurate slicer (sign-detector). Then the principle of operation amounts to binary search starting with full scale and halving up the interval d=B−1 times. SAR ADCs are not actually used in electronics with b>1, however for the purpose of the current invention, it is of interest to consider such “higher-order” SAR, as it is the basis for the optical SAR realization according to the current invention.
FIG. 2a(ii) schematically depicts the first two steps of SAR process for b=2 case (two bits ADC)
Now the ADC must have an adaptive full scale, starting with the full-scale 130 of the voltage under test and scaling down its full-scale in each cycle by a factor of 2b. This calls for the ability to modify the positions of the 2b ADC thresholds gnU, which will be seen possible in the inventive PADC case. Practically, this cannot be continued indefinitely, as the thresholds get too close together, becoming hard to resolve. The SAR operates as follows: starting with the full scale 130, each recursive interval is segmented in 2b intervals, to generate a new sub-intervals 130′; 130″, etc., and the signal under test is determined to be in one of these 2b intervals by virtue of the b-hits ADC action. Then the DAC subtracts in the n-th stage the “baseline” (BL[n]) of the recursive interval just found off the signal (the “baseline” is either the center of the interval or the bottom value of the interval, depending on the type of ADC), then another cycle of b-bits ADC is performed (with a 2b times more compressed full-scale), pinpointing the signal under test to a new sub-interval. Again the baseline of the new sub-interval is subtracted off from the voltage under test by the DAC, and the process is repeated, zooming in deeper.
FIG. 2(b) schematically described a block diagram of a cyclic ADC 130 as known in the art.
This structure is very similar to the SAR ADC 120 (in fact the CYC 135 logic is virtually identical to the SAR logic 125), except that the difference output is rescaled 139 by a factor G=2b, prior to being ADC-ed, hence the ADC 137 does not need to have an adaptive full scale, but can have a fixed full scale. Evidently this is preferable to the SAR ADC, but unfortunately, we cannot apply such scaling in our photonic implementation, hence we shall not be able to realize the cyclic ADC but just the SAR ADC.
FIG. 3 schematically depicts a block diagram 140 of a Pipelining ADC.
It may be described as a spatially laid out version of the Cyclic ADC. Each stage, such as stages 141(1), 141(2) and 141(3) generates a partial decision (respectively 142(1), 142(2) and 142(3) being the Most Significant Bits (MSBs), Medium Significant Bits (mSBs); and Least Significant Bits (LSBs)), on some of the ADC bits, as well as a residual error. The error is in turn amplified 143(1) and 143(2) by a factor of 2b wherein b is the number of bits of the ADC and DAC to form the input V(1)RES(t) and V(2)RES(t) of stages 141(2) and 141(3) respectively. Inputs V(1)RES(t) and V(2)RES(t) are then requantized again in the following section, and so on.
FIG. 4 schematically depicts a block diagrams 5 exemplary variations of Sigma-Delta (ΣΔ) ADC
A ΣΔ ADC is a system sampling its input at a much higher rate (dΣΔ×) than the Nyquist sampling rate by means of the ΣΔ “modulator” module, followed by the decimator (DEC) module, bringing the rate down by the integer factor of dΣΔ, in order to gain in quantization noise shaping.
We only consider here a first-order ΣΔ ADC, using an analog integrator (INT) or analog accumulator (ACC) in the loop. It turns out that the improvement in the ENOB factor in the first-order filtering case is 1.5 log2 dΣΔ i.e. 1.5 bits for each octave (doubling) of the rate. The figures show several variants, some of which are of theoretical interest. In FIGS. 4A, 4B, and 4C a T&H is used in the first stage, hence the modulator actually describes a discrete-time system, acting on the analog-valued discrete-time samples generated by the T&H.
The basic mathematical structure of FIG. 4A is with all the signals within the modulator being stylized as discrete-time sequences.
In operation, the sampler “SAMP” performs analog sampling of the input voltage νUT(t) at regular times t=T*k, producing series of analog samples νκ. Synchronization is maintained by a clock (CLC), producing a pulse “k” at these regular time intervals “T”.
After analog subtraction at subtractor Σ, of the output dk of the Digital to Analog Converter DAC, the voltage at the input to the accumulator ACC is given by εk.
The accumulator ACC performs analog accumulation of the signal εk. producing a sum signal Sεk so that:εk=νk−dk; skε=Σk′=0kεk′=sk-1ε+εk-1.
Analog accumulator ACC accumulates the residual signals εk to produce the accumulated signal Sεk.
Accumulated signal Sεk is digitized by a fast analog to digital converter ADC.
The digital results of ADC are converted back to analog signal dk to be subtracted from the sampled input signal. Due to the small number of bits of ADC, the signal dk is generally smaller than sample νk. However, the residual difference is not lost, but remain in the subtracted residual signal dk to be accumulated at the ACC.
After one or few cycles, the accumulated residuals dk+dk+1+, . . . may add up to influence the result of ADC.
Decimator DEC receives it synchronization k/N from a cyclic counter N, reducing the rate of clock CLC by a factor of N. Decimator DEC digitally adds up the digital results Dk of analog to digital converter DEC produced in the time interval t=T*k*N to t=T*k*(N+1) and presents at the output B(k/n) at the “bits out” digital output.
It is easy to see that if the resolution of ADC and DAC is 2n, where n is the number of bits of ADC and DAC, than the resolution given by DEC is N*2n.
A discussion of a one-bit case may be seen for example in http://en.wikipedia.org/wiki/Delta-sigma modulation.
In FIG. 4B we find it convenient to pull up the ACC ahead of the subtractor Σ, hence replacing the sole ACC within the loop in FIG. 4A with a pair of ACCs: ACC1 at the input and ACC2 within the loop, the outputs of which are subtracted at subtractor Σ.
For clarity, the clock subsystem and sum of the markings are not drawn in this figure.
The version in FIG. 4C is a more realistic one, representing now the outputs of the Track and Hold (T&H) and the digital to analog DAC&H not as discrete-time sequences but as “shift-invariant” analog continuous-time signals ν(t)=Σkνkh(t−kT) and d(t)=Σkdkh(t−kT), respectively, where h(t) is a “hold” pulse shape, e.g. a rectangle for a zero-order-hold (ZOH). Let us make the assumption that h(t) has support [0,T], and its integral is normalized to unity ∫−∞−∞h(t′)dt′=∫0Th(t′)dt′=1.
The accumulator is now replaced by an analog integrator, generating
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Notice that the digital to analog converter DAC&H and analog to digital converter ADC now incorporates a holding function. Analog to digital converter ADC ideally generates the samples sε(kT), which are readily evaluated at the discrete times by setting t=kT in the last equation: sε(kT)=Σk′εk′∫−∞kTh(t′−k′T)dt′. It is readily seen that under the assumptions on h(t), the integral in the last expression is given by ∫−∞kTh(t′−k′T)dt′=1 if k′≦k−1, ∫∞kTh(t′−k′T)dt′=0 otherwise. Then ∫∞kTh(t′−k′T)dt′=uk-1-k′ where uk is a discrete-time step function. Then, sε(kT)=Σk′εk′uk 1 k′=Σk′-∞k-1εk′=skε, i.e. we have established that the system in FIG. 4C is equivalent to those in FIGS. 4A and 4B.
As for the systems in FIGS. 4D and 4E which are evidently equivalent to each other, it is possible to show their equivalence to the previous ones. Specifically this is the case if the input νUT(t) is bounded to a certain level which depends on the full scale of the ADC, and the area under the DAC pulse.
We have normalized the area under the DAC pulse to unity, and let us further assume that the full scale range of the ADC is [−1,1]. The condition on νUT(t) is then that its integral over consecutive T seconds intervals, where T−1 is the oversampling rate, be bounded by unity, a sufficient (but not necessary) condition for which is that the input signal νUT(t) be bounded as |νUT(t)|<T−1.
Overview of Existing Opto-Electronic Approaches to Analog-to-Digital Conversion
In an effort to achieve higher-performance ADCs, there have been a number of applications of photonic technologies to the problem of A/D conversion. Our survey the existing photonic principle of analog to digital conversion revealed a large number of optically-related architectures, studied over the past 30 years. Starting with the early 70's, researchers provided some proof-of-concept of ADCs taking advantage of interesting optical properties. The comprehensive 2007 survey of photonic ADCs architectures by Valley [1] (available online) is recommended as an excellent review source quoting, summarizing and classifying over 150 papers. Valley proposes to classify the existing photonic ADC architectures in 4 groups (all these architectures assume an electronic analog input and an electronic digital output, with photonics inside):
(i) photonic-assisted
(ii) photonic sampled (electronically quantized)
(iii) Photonic quantized (electronically sampled)
(iv): photonic sampled and quantized
The systems according to the current invention fall into class (iv) but work on an a new principle displaying much improved characteristics relative to all-photonic quantization approaches published so far, to the best of our knowledge. Henceforth when referring to Photonic ADC (PADC) we mean a class-(iv) system, photonic sampled and quantized, with electrical analog input and electrical digital output Below we briefly survey some representative systems out of the four classes of photonic-related ADCs.
FIG. 5(i) shows some details of a photonic ADC system 500 which is one of the earliest systems that were developed by Taylor in 1975 [10] For clarity, only some of elements “a” to “d” referring to equivalent elements of system 500 and signals in graph 550 in FIGS. 5(i) and 5(ii) may be marked in these figures.
Photonic ADC system 500 receives electrical input signal VRF 520, which is amplified 521 and is fed to electrodes 512 affecting relative phase shifts in the arms of electro-optic Mach-Zehnder (MZ) modulators 510a to 510d. The MZ modulators are formed by creating wave-guiding traces 523 on a substrate 524. A mode-locked laser 525 provides a train of short, coherent, intense optical pulses at regular time intervals.
He recognized that the periodicity of the corresponding outputs 511a to 511d of an interferometric electro-optic Mach-Zehnder (MZ) modulators 510a to 510d are homomorphic to the periodic variation of the binary representation of an analog quantity, and therefore proposed a scheme based on multiple MZ modulators with lengths of electrodes 512a to 512d forming a binary sequence, with their outputs photo-detected by Avalanche Photo Diodes (APDs) 513a-d, amplified 514a-d, and compared against a threshold 517 in comparators 515a-d. 
FIG. 5(ii) shows the photocurrents I1, I2, I3 and I4, detected by APDs 513a-d respectively vs. input voltage VRF.
Since the transfer characteristic 551a-c of a MZ 510a-c is sinusoidal with period inversely proportional to the switching voltage hence inversely proportional to the length of the corresponding electrode 512, it has a sinusoidal transfer characteristics shown in FIG. 5(ii) (output photocurrent vs. input voltage), which after thresholding half way between on and off voltages, appear like square wave transfer characteristics 553a-d with periods forming a power-of-two sequence. It is readily seen that passing an input voltage under test through such a bank of memory-less transfer characteristics yields the Gray code binary representation of the input voltage 520 under test.
An improvement was suggested by Jalali and Xie [11] eliminating the binary scaling of the MZ electrodes by incorporating an analog coding technique. This scheme is susceptible to noise from extreme values of the input, and it relies on the ability to accurately bias multiple MZ modulators to certain operating points, and the number of MZ required is 2^(b−2)+1, with b the resolution in bits. We mention in particular these modulator-array based schemes (and there are many other variations based on the same underlying principles, as surveyed in [2]) since superficially they resemble what the embodiments of the current invention do. Both are based on electro-optic modulation and a relatively complex Programmable Logic Controller (PLC), but the principle of operation and ensuing qualities of the current invention are totally different.
Tsunoda and Goodman [12]proposed an approach to optical ADC based on matrix multiplication and acousto-optic beam deflection. Diverse photonic ADC system approaches, are also described in some detail in [1-3].
Recently, there has been intensive work on time-stretching ADCs [1], which can sample ultra-high rate signals but require extremely complex and large extent optical setups, and have difficulty in digitizing continuous signals, but work best with burst signals.
There has recently been work on all-optical ADC and DAC [13,14], however at this point we deem those approaches as more futuristic, as we are aiming for electronic ADCs which are internally assisted by photonics.
Notice that Valley's survey does not cover all-optical ADCs (with the analog input digital output both photonic) which have been discussed in [13] and more recently in [14], however our current position is that all-photonic ADC is a more futuristic technology and we wish to focus on class (iv) photonic ADCs with electrical interfaces.
Notice that most of the PADC advances in the last 30 years have occurred in the field of photonic sampling, which has nicely progressed, however the photonic quantization approaches offered so far remain inadequate. Our comparison benchmark for the resulting performance of our novel class (iv) photonically sampled & quantized PADC, will then be provided by a “conventional” class (ii) photonically sampled (electronically quantized) PADC system.
For a review of the state-of-the-art of photonic ADC see Valley's 2007 review paper [1], surveying over 150 papers on photonic on photonic sampling and/or photonic quantization. See also [2,3] for earlier contributions.